Intrinsic-ID
iRNG: 
iRNG News


04/19/2011
Electronic Engineering Journal, 'You Got It, They Want It' by Jim Turley
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04/07/2011
Intrinsic-ID, today announced iRNG, a true Random Number Generator delivered as hardware IP (RTL) or embedded software.
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iRNG Random Number Generator brochure

 

 

iRNG

 


Intrinsic-ID’s iRNG is a random number generator developed on Intrinsic-IDs Hardware Intrinsic Security (HIS) technology. The generation of random data by iRNG is based on the use of memory:  6T-SRAM is used as the source of entropy. This uninitialized SRAM is used for the generation of a true random seed, which serves as input for a FIPS 140-3 compliant Deterministic Random Bit Generator (DRBG). It is designed to generate large amounts of random data at high speed, with a very short start-up time. It is available both in hardware and software and can be integrated seamlessly into any chip design. 

Functionality: 

Random data generation

Advantages:

  • Quick start-up time, due to always ready SRAM
  • Fast generation of large amounts of random data
  • Based on true random seed
  • Technology based on uninitialized SRAM makes the device unclonable
  • Low implementation cost
  • Usage of the SRAM makes the technology scalable, small and flexible towards process  variations.
  • iRNG has a high reliability, several tests have been performed and its behavior is stable under all circumstances (changes in temperature, voltage, aging).

Applications:

  • For a complete security solution, iRNG can be combined with other products of Intrinsic-ID, e.g. Quiddikey. With this completely HIS-based security functionality, no secret information leaves the device unprotected.
  • The generated random bit stream is approved to be used for the generation of strong key material, IVs, nonces and any other random data.
  • iRNG can be used in many kinds of devices and applications such as smart cards, automotive ICs, government & military communication systems, content protection systems, routers or other network communication devices, Public Key Infrastructures, modules for erasing sensitive data by overwriting with random data, etc.


Hardware Specification Example

Process 90 nm, TSMC
Number of gates ±10k
SRAM ±2kbyte
Performance 4 cycles per byte;
200Mbit/sec
@100MHz
Startup cycles ~20kcycles; 0.2ms
@100MHz
Max. random bits before repowering <264
Area <0.1mm2

 

Software Specification Example

 
Platform ARM Cortex-M3
SRAM ~2kBytes
Performance

0.3ms for 16 bytes
0.22Mbit/sec
@25Mhz

Startup cycles

~3.7Mcycles
149ms @25MHz

Max. random bits before repowering <264

 


Intrinsic-ID Inc.
2033 Gateway Place, Suite 500
San Jose, CA 95110
USA
+1 408-573-6186

Intrinsic-ID B.V. Headquarters
High Tech Campus 9
5656 AE Eindhoven
The Netherlands
+31 40 851 90 20

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