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QuiddiKey RNG

Random number generators (RNGs) are essential in many cryptographic operations. For example, RNGs are used to secure connections on the internet of things (IoT), or in automotive or datacenter settings. Intrinsic ID QuiddiKey® RNG is a hardware IP solution compliant with the NIST SP 800-90 standard that implements a chained RBG construction with deterministic random bit generators (DRBG) as specified in NIST SP 800-90A. The RBG is seeded by a true-random seed that is harvested from the noise in an SRAM physical unclonable function (PUF). This construction follows the NIST SP 800-90B specification.

SRAM PUFs use the behavior of standard SRAM, available in any digital chip, to extract entropy. They are virtually impossible to duplicate, clone or predict. This makes them very suitable for applications that require high-quality random numbers to be used as strong key material, initialization vectors (IVs), nonces, etc. QuiddiKey RNG is technology-independent and can be added easily to almost any chip – from tiny microcontrollers (MCUs) to high-performance systems-on-chip (SoCs).

QuiddiKey RNG Diagram


  • Supplies 256-bit random entropy
  • Uses standard SRAM power-up values as a true random source
  • Includes built-in self test
  • Eases integration with a custom driver API
  • Complies with NIST SP 800-90A/B


  • Can be added easily to almost any chip – from tiny MCUs to high-performance SoCs
  • Foundry- and technology node independent
  • Supports FIPS 140-3 certification
  • Includes attack countermeasures
  • Remains secure post quantum computing


  • Content protection
  • Authentication
  • Secure communications
  • Platform security


  • NIST CAVP for DRBG, HMAC, SHA – pending
  • NIST SP 800-90A/B compliant
  • Supports FIPS140-3 certification

QuiddiKey RNG Configuration

QuiddiKey RNG


Security strength (bits)


Logic (gates)


SRAM required (bytes)


Time-to-output (cycles)




Logic BIST

Attack countermeasures

NIST SP 800-90A compliant DRBG
• Health checks
• Reseed counter
• Test interface

NIST SP 800-90B compliant entropy source
• Entropy model and proof

External DRBG instantiate


Reseed required after

2^48 requests

(✓) features are optional

Operational Range

The Intrinsic ID PUF-based solutions have been deployed on MCUs/SoCs/ASICs in a diverse set of foundry/process node combinations. SRAM PUF responses across this diverse array have been qualified for use in a wide range of operational environments, over years of field operation.

QuiddiKey Reliability Image

QuiddiKey RNG Deliverables

QuiddiKey RNG IP can be integrated easily into any semiconductor design across all foundries and process nodes. Standard deliverables include:

  • RTL netlist (VHDL, Verilog)
  • APB interface
  • Testbench (UVM + VHDL)
  • Synopsys Design Compiler® synthesis constraints (tcl)
  • Register description (IP-XACT)
  • Driver (C sources, headers)
  • Documentation
  • C Model
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