Intrinsic ID QuiddiKey® is a hardware IP solution that enables device manufacturers and designers to secure their products with internally generated, device-unique cryptographic keys without the need for adding costly, security-dedicated silicon. It uses the inherently random start-up values of SRAM as a physical unclonable function (PUF), which generates the entropy required for a strong hardware root of trust. QuiddiKey IP can be applied easily to almost any chip – from tiny microcontrollers (MCUs) to high-performance systems-on-chip (SoCs).
SRAM is a standard component available upon initial release of any process technology; because it uses SRAM as a PUF source, the IP can be used with any foundry and process-node technology. QuiddiKey has been validated for NIST CAVP and has been deployed and proven in hundreds of millions of devices certified by EMVCo, Visa, CC EAL6+, PSA, ioXt, and governments across the globe.
- Uses standard SRAM start-up values as a PUF to create a hardware root of trust
- Root key is never stored, but re-created from the PUF each time it is needed
- Offers key provisioning, wrapping, and unwrapping to enable secure key storage across the supply chain and for the lifetime of the device
- Keys are bound to the device and can only be recreated and accessed on the device they have been created on
- Configurations can be customized for your application
- Custom driver API for easy integration
- Deployed in hundreds of millions of production devices over more than a decade
- Offers a higher level of security than traditional key storage in NVM such as secure flash, OTP or e-fuses
- Enables designers to create and store an unlimited number of keys securely in unprotected NVM on/off chip
- Minimizes overhead through optimized hardware design
- Eliminates the need for centralized key management and programming
- Highly reliable secure key storage solution in the most advanced technology nodes
Why You Need QuiddiKey
Secure supply chain: Each QuiddiKey user can generate an unlimited number of device-unique keys. None of these keys are ever stored on the device. This means that each user in the supply chain can derive their own device-unique keys and import and protect other secrets, without these keys or secrets being known to the manufacturer or other supply-chain users. The wrapping functionality enables supply-chain applications and IP to be securely and reliably protected – for the lifetime of the device – prior to being deployed in the field.
Protection against reverse-engineering, counterfeiting/cloning: QuiddiKey protects firmware IP by encrypting it with a PUF-derived encryption key that is locked to the hardware instance of the device. If the firmware IP tied to a device with QuiddiKey is copied to other device instances, these rogue devices cannot unlock the IP or use it, because every device has a different hardware fingerprint.
Other use cases: Secure key storage, flexible key provisioning, HW-SW binding, secure communication, authentication
QuiddiKey is available in off-the-shelf configurations with size ranging between 39k and 72k gates. Configurations differ according to functionality, performance and compliance, enabling options customized to the needs of your application (options are shown in parentheses in the chart, below; configurations that include options will have gate-counts at the higher end of the range).
|Generate device-unique keys||
|Generate random values||
|Wrap and unwrap keys||
|Size (k gates)||
|AC size (bytes)||
|Security strength (bits)||
|Maximum key length (bits)||
|Time to root key (k cycles)||
|SRAM required for PUF (kB)||
|NIST CAVP certification (DRBG, AES, KDF)||
|NIST SP 800-90 compliant||
APB / TileLink-UL
|Masked key output||
|SRAM health checks||
(✓) features are optional
QuiddiKey has been deployed on MCUs/SoCs/ASICs in a diverse set of foundry/process node combinations. SRAM PUF responses across this diverse array have been qualified for use with QuiddiKey in a wide range of operational environments, over years of field operation.
QuiddiKey IP can be integrated easily into any semiconductor design across all foundries and process nodes. Standard deliverables include:
- RTL netlist (Verilog, VHDL)
- Testbench (UVM, VHDL)
- C model
- APB or TileLink interface (VHDL, Verilog)
- Design Compiler synthesis constraints (tcl)
- QuiddiKey Driver (C sources, headers)
- QuiddiKey register description (IP-XACT)
- Datasheet, integration manual and driver documentation
- NIST documentation (SP 800-90A/B)
Driver Eases Integration
The QuiddiKey driver eases the use of the HW IP for developers in an embedded software environment. It is delivered as C source code and comes with a reference manual, integration tests and the QuiddiKey register description.